In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The receiving bus nodes recognize the signal as being high or low using receivers, also referred to as input buffers. Often the receiver is a differential receiver, i.e., a receiver that detects the difference between two input signals, referred to as the differential inputs. These input signals may be a received signal and a reference voltage or they may be a received signal and the inverse of the received signal. In either case, it is the difference between the two input signals that the receiver detects in order to determine the state of the received signal.
Integrated circuits are powered at certain voltage levels, which levels are then provided to the various components, such as the receivers, which are located on the integrated circuit. However, the nominal supply voltage for integrated circuits keeps being decreased to reduce power consumption. Additionally, fluctuations of the voltage level during operation can make the voltage level powering a receiver even lower. The lower the supply voltage, the more challenging it is to get a receiver to operate reliably.
The signal frequency at which communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to be reliably recognized at the receiving bus nodes as being high or low. Characteristics that affect the time in which a signal is recognized by a receiver include the set up time of the receiver, i.e., the amount of time before a clock edge that a signal must arrive and settle to a recognized level, and the hold time of the receiver, i.e., the time that the received signal must stay at a certain level in order for that level to be detected by the receiver.
Other characteristics that affect the ability of the receiver to determine that state of the received signal include the ability of the receiver to reject input noise and power supply noise and sensitivity, i.e., the ability of the receiver to resolve small voltage differences between the differential inputs of the receiver. There are many kinds of receivers, inverters, differential amplifiers, and sense amplifiers. Sense amplifier type input receivers have the advantage of good sensitivity, i.e., almost zero setup time and a specific hold time. These features improve timing for high speed I/O interfaces.
Output from a sense amplifier, or other clock-like signal, is delivered to a global bitline through a driving stage as shown in FIG. 1. The sense amplifier output (sao) fed into an nmos transistor (MN1) coupled between another nmos transistor and a pmos transistor. The pmos transistor (MP) is coupled to Vcc and receives the delayed clock signal 1 (dclk1). The nmos transistor (MN2) is coupled to ground (GND) and receives the delayed clock signal 2 (dclk2). The global bitline (gbit) is coupled to the driving stage between the pmos transistor (MP) and the nmos transistor (MN1). The sense amplifier output is derived on the high to low transition of the clock signal (clk), i.e., the b-phase. However, the sense amplifier output (sao) may change so slowly that the clock signal (clk) has transitioned low to high, i.e., the a-phase, before the change occurs.
Those skilled in the art will appreciate that when a driver and precharge of a signal is driven by different signals, the driver has to turn off before the precharge begins and precharge has to end before the driver turns on. If not, crowbar current will flow between the precharge and driver transistors, and the output may not be driven or precharged to rail voltages. Thus, clock skew has to be accounted for in order to avoid these conditions.
The above configuration is commonly known as a footer device scheme because it includes the pull down transistor (MN2). In a footer device scheme, in order to attain the same drive strength as a non-footer scheme, the driver device size has to increase. Further, the footer device increases the clock loading.
If there are multiple drivers and precharge on the same signal (wired-or structure), with the drivers and precharges driven by more than one clock grid, the clock skew may become so large that the window for driving and precharge of the signal becomes very narrow. To compensate for this narrowed window, the driver and precharge transistor sizes often is increased. Even then, at some point, the return is diminished because the increased diffusion capacitance of the now larger transistors causes self-loading on the signal. Thus, regardless of how large the transistors sizes are increased thereafter, the signal does not speed up.
In general, in one aspect, a system for minimizing the effect of clock skew in a precharge circuit comprises a switch coupled between an input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated and the control circuit receives feedback from the switch.
In general, in one aspect, a method of minimizing the effect of clock skew in a precharge circuit comprises controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; controlling the outputting of the second signal from the precharge circuit based on feedback of the first signal; and controlling the outputting of the first signal from the switch based on a clock signal, a select signal, and a dynamic signal.
In general, in one aspect, an apparatus for minimizing the effect of clock skew in a precharge circuit comprises means for controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; means for controlling the outputting of the second signal from the precharge circuit based on feedback of the first signal; and means for controlling the outputting of the first signal from the switch based on a clock signal, a select signal, and a dynamic signal.
In general, in one aspect, a system for minimizing the effect of clock skew in a precharge circuit comprises a switch coupled between input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated, the control circuit receives feedback from the switch, and the precharge component receives feedback from the switch and the global bitline.
In general, in one aspect, a system for minimizing the effect of clock skew in a precharge circuit comprises a switch coupled between a first input to the precharge circuit and a global bitline and a second input to the precharge circuit and a global bitline; a first control circuit coupled to a precharge component and the switch, and a second control circuit coupled to a precharge component and the switch. The first control circuit determines whether the switch and the precharge component are activated for the first input, the second control circuit determines whether the switch and the precharge component are activated for the second input, the first control circuit receives feedback from the switch, the second control circuit receives feedback from the switch, and the precharge component receives feedback from the switch and the global bitline.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.